1. Field
This disclosure relates generally to integrated circuits, and more specifically, to semiconductor device having a test controller.
2. Related Art
Register-based testing of system-on-a-chip (SoC) allows for register-configured testing which may include, for example, the use of self tests to test and trim analog circuits. Currently, register-based testing may be performed using either a slave test port or a master mode test. With a slave test port, the SoC includes a slave test port in which an external tester is the master and has access to read and write registers of peripherals of the SoC, in which these accesses by the external tester are synchronous with the SoC. For example, the slave test port may provide access to the system bus of the SoC. However, in the case of a slave test port, the test data has to be serially transferred to the external tester for any determination to be made on the test data, such the pass/fail status or best trim values. This increases test time. With a master mode test, the processor of the SoC executes code from a random access memory (RAM) of the SoC. The code allows for the processor to perform processor functions but is not synchronized to an external tester. This requires the external tester to be more aware of the SoC testing and also reduces testing visibility. Therefore, a need exists for improved SoC testing.